Chua-Chin Wang, Ya-Hsin Hsueh, Yu-Tsun Chien, Ying-Pei Chen. Design of an Inter-plane Circuit for Clocked PLAs. VLSI Design, 2002(4):373-381, 2002. [doi]
@article{WangHCC02-0,
title = {Design of an Inter-plane Circuit for Clocked PLAs},
author = {Chua-Chin Wang and Ya-Hsin Hsueh and Yu-Tsun Chien and Ying-Pei Chen},
year = {2002},
doi = {10.1080/10655140290011186},
url = {http://dx.doi.org/10.1080/10655140290011186},
researchr = {https://researchr.org/publication/WangHCC02-0},
cites = {0},
citedby = {0},
journal = {VLSI Design},
volume = {2002},
number = {4},
pages = {373-381},
}