Zhe Wang, Daniel A. Jiménez, Tao Zhang, Gabriel H. Loh, Yuan Xie. Building a Low Latency, Highly Associative DRAM Cache with the Buffered Way Predictor. In 28th International Symposium on Computer Architecture and High Performance Computing, SBAC-PAD 2016, Los Angeles, CA, USA, October 26-28, 2016. pages 109-117, IEEE Computer Society, 2016. [doi]
Abstract is missing.