Zhaowen Wang, Peter R. Kinget. A 65nm CMOS, 3.5-to-11GHz, Less-Than-1.45LSB-INLpp, 7b Twin Phase Interpolator with a Wideband, Low-Noise Delta Quadrature Delay-Locked Loop for High-Speed Data Links. In IEEE International Solid-State Circuits Conference, ISSCC 2022, San Francisco, CA, USA, February 20-26, 2022. pages 292-294, IEEE, 2022. [doi]
@inproceedings{WangK22a,
title = {A 65nm CMOS, 3.5-to-11GHz, Less-Than-1.45LSB-INLpp, 7b Twin Phase Interpolator with a Wideband, Low-Noise Delta Quadrature Delay-Locked Loop for High-Speed Data Links},
author = {Zhaowen Wang and Peter R. Kinget},
year = {2022},
doi = {10.1109/ISSCC42614.2022.9731649},
url = {https://doi.org/10.1109/ISSCC42614.2022.9731649},
researchr = {https://researchr.org/publication/WangK22a},
cites = {0},
citedby = {0},
pages = {292-294},
booktitle = {IEEE International Solid-State Circuits Conference, ISSCC 2022, San Francisco, CA, USA, February 20-26, 2022},
publisher = {IEEE},
isbn = {978-1-6654-2800-2},
}