Low-Power VLSI Design of LDPC Decoder Using Dynamic Voltage and Frequency Scaling for Additive White Gaussian Noise Channels - researchr publication

researchr

You are not signed in
Sign in
Sign up

Weihuang Wang, Euncheol Kim, Kiran K. Gunnam, Gwan S. Choi. Low-Power VLSI Design of LDPC Decoder Using Dynamic Voltage and Frequency Scaling for Additive White Gaussian Noise Channels. J. Low Power Electronics, 5(3):303-312, 2009. [doi]

Abstract is missing.

runs on WebDSL