The following publications are possibly variants of this publication:
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- A 40nm 256kb 6T SRAM with threshold power-gating, low-swing global read bit-line, and charge-sharing write with Vtrip-tracking and negative source-line write-assistsChao-Kuei Chung, Chien-Yu Lu, Zhi-Hao Chang, Shyh-Jye Jou, Ching-Te Chuang, Ming-Hsien Tu, Yu-Hsian Chen, Yong-Jyun Hu, Paul-Sen Kan, Huan-Shun Huang, Kuen-Di Lee, Yung-Shin Kao. socc 2014: 455-462 [doi]
- Low write-energy STT-MRAMs using FinFET-based access transistorsAlireza Shafaei, Yanzhi Wang, Massoud Pedram. iccd 2014: 374-379 [doi]
- An experimental 295 MHz CMOS 4K/spl times/256 SRAM using bidirectional read/write shared sense amps and self-timed pulsed word-line driversNatsuki Kushiyama, Charles Tan, Richard Clark, Jane Lin, Fred Perner, Lisa Martin, Mark Leonard, Gene Coussens, Kit Cham. jssc, 30(11):1286-1290, November 1995. [doi]