DART: A Programmable Architecture for NoC Simulation on FPGAs

Danyao Wang, Charles Lo, Jasmina Vasiljevic, Natalie D. Enright Jerger, J. Gregory Steffan. DART: A Programmable Architecture for NoC Simulation on FPGAs. IEEE Transactions on Computers, 63(3):664-678, 2014. [doi]

@article{WangLVJS14,
  title = {DART: A Programmable Architecture for NoC Simulation on FPGAs},
  author = {Danyao Wang and Charles Lo and Jasmina Vasiljevic and Natalie D. Enright Jerger and J. Gregory Steffan},
  year = {2014},
  doi = {10.1109/TC.2012.121},
  url = {http://doi.ieeecomputersociety.org/10.1109/TC.2012.121},
  researchr = {https://researchr.org/publication/WangLVJS14},
  cites = {0},
  citedby = {0},
  journal = {IEEE Transactions on Computers},
  volume = {63},
  number = {3},
  pages = {664-678},
}