The following publications are possibly variants of this publication:
- Optimal two level partitioning and loop scheduling for hiding memory latency for DSP applicationsZhong Wang, Michael Kirkpatrick, Edwin Hsing-Mean Sha. dac 2000: 540-545 [doi]
- Loop Scheduling and Partitions for Hiding Memory LatenciesFei Chen, Edwin Hsing-Mean Sha. isss 1999: 64-70 [doi]
- Iterational retiming with partitioning: Loop scheduling with complete memory latency hidingChun Jason Xue, Jingtong Hu, Zili Shao, Edwin Hsing-Mean Sha. tecs, 9(3), 2010. [doi]
- Minimizing Average Schedule Length under Memory Constraints by Optimal Partitioning and PrefetchingZhong Wang, Timothy W. O Neil, Edwin Hsing-Mean Sha. vlsisp, 27(3):215-233, 2001. [doi]
- Optimizing Overall Loop Schedules Using Prefetching and PartitioningFei Chen, Timothy W. O Neil, Edwin Hsing-Mean Sha. tpds, 11(6):604-614, 2000. [doi]
- Partitioning and Scheduling DSP Applications with Maximal Memory Access HidingZhong Wang, Edwin Hsing-Mean Sha, Yuke Wang. ejasp, 2002(9):926-935, 2002. [doi]