A new architecture of RRNS error-correcting QC encoder/decoder and its FPGA implementation

Wei Wang 0003, M. N. S. Swamy, M. Omair Ahmad. A new architecture of RRNS error-correcting QC encoder/decoder and its FPGA implementation. In ISCAS (4). pages 813-816, 2002. [doi]

@inproceedings{WangSA02,
  title = {A new architecture of RRNS error-correcting QC encoder/decoder and its FPGA implementation},
  author = {Wei Wang 0003 and M. N. S. Swamy and M. Omair Ahmad},
  year = {2002},
  doi = {10.1109/ISCAS.2002.1010828},
  url = {http://doi.ieeecomputersociety.org/10.1109/ISCAS.2002.1010828},
  tags = {architecture},
  researchr = {https://researchr.org/publication/WangSA02},
  cites = {0},
  citedby = {0},
  pages = {813-816},
  booktitle = {ISCAS (4)},
}