Wei Wang 0003 - researchr alias

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Viewing Publication 1 - 20 from 20

2024

OGIG: A Botnet Detection Model Integrating Graph Structural Modeling and Time Series AnalysisWei Wang 0003, Ying Yang, Yangzhi Hou, Zhaoyong Yu, Wenhao Ma. icbase 2024: 561-564 [doi]

2015

Climate Analytics Workflow Recommendation as a Service - Provenance-Driven Automatic Workflow MashupJia Zhang, Wei Wang 0003, Xing Wei, Chris Lee, SeungWon Lee, Lei Pan, Tsengdar J. Lee. icws 2015: 89-97 [doi]

2012

Effects of Copper Plasticity on the Induction of Stress in Silicon from Copper Through-Silicon Vias (TSVs) for 3D Integrated CircuitsBenjamin Backes, Colin McDonough, Larry Smith, Wei Wang 0003, Robert E. Geer. et, 28(1):53-62, 2012. [doi]

2011

FPGA Based on Integration of CMOS and RRAMSansiri Tanachutiwat, Ming Liu, Wei Wang 0003. tvlsi, 19(11):2023-2032, 2011. [doi]

2009

FPGA based on integration of carbon nanorelays and CMOS devicesMing Liu, Haigang Yang, Sansiri Tanachutiwat, Wei Wang 0003. NANOARCH 2009: 61-64 [doi]

2008

rFGA: CMOS-nano hybrid FPGA using RRAM componentsMing Liu, Wei Wang 0003. NANOARCH 2008: 93-98 [doi]

2007

3-D nFPGA: A Reconfigurable Architecture for 3-D CMOS/Nanomaterial Hybrid Digital CircuitsChen Dong, Deming Chen, S. Haruehanroengra, Wei Wang 0003. tcas, 54-I(11):2489-2501, 2007. [doi]

Hardware Organization to Achieve High-Speed Elliptic Curve Cryptography for Mobile DevicesSining Liu, Brian King, Wei Wang 0003. monet, 12(4):271-279, 2007. [doi]

2006

On-Chip Interconnects and Repeaters Based on NiSi NanowiresWei Wang 0003, Adam Maina Ari, Woon Ket Wong. nanonet 2006: 1-5 [doi]

Elliptic curves cryptosystem implementation based on a look-up table sharing schemeSining Liu, F. Bowen, Brian King, Wei Wang 0003. iscas 2006: [doi]

A CRT-RSA Algorithm Secure against Hardware Fault AttacksSining Liu, Brian King, Wei Wang 0003. dasc 2006: 51-60 [doi]

2005

RRNS Quasi-Chaotic Coding and Its FPGA ImplementationWei Wang 0003, Xiaolin Zhang, Chenyang Yang, M. N. S. Swamy, M. Omair Ahmad. snpd 2005: 274-280 [doi]

An Area-Reduced Scheme for Modulo 2n-1 Addition/SubtractionShaoqiang Bi, Warren J. Gross, Wei Wang 0003, Asim J. Al-Khalili, M. N. S. Swamy. iwsoc 2005: 396-399 [doi]

2004

2003

Moduli selection in RNS for efficient VLSI implementationWei Wang 0003, M. N. S. Swamy, M. Omair Ahmad. iscas 2003: 512-515 [doi]

2002

A new architecture of RRNS error-correcting QC encoder/decoder and its FPGA implementationWei Wang 0003, M. N. S. Swamy, M. Omair Ahmad. iscas 2002: 813-816 [doi]

1999

A high-speed residue-to-binary converter and a scheme for its VLSI implementationWei Wang 0003, M. N. S. Swamy, M. Omair Ahmad, Yuke Wang. iscas 1999: 330-333 [doi]

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