Yiting Wang, Guoheng Sun, Wanghao Ye, Gang Qu 0001, Ang Li 0005. VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generation. In Fan Chen 0001, Peipei Zhou 0001, Jie Gu 0001, Amit Ranjan Trivedi, Xiaoxuan Yang 0001, editors, Proceedings of the Great Lakes Symposium on VLSI 2026, GLSVLSI 2026, Canandaigua, NY, USA, June 22-24, 2026. pages 948-953, ACM, 2026. [doi]
Abstract is missing.