A 64-Gb/s 0.33-pJ/bit PAM4 Receiver Analog Front-End with a Single-Stage Triple-Peaking CTLE Achieving 22.5-dB Boost in 40-nm CMOS Process

Guoqing Wang, Zhao Zhang 0004, Xinyu Shen, Zhaoyu Zhang, Jian Liu 0021, Nanjian Wu, Liyuan Liu. A 64-Gb/s 0.33-pJ/bit PAM4 Receiver Analog Front-End with a Single-Stage Triple-Peaking CTLE Achieving 22.5-dB Boost in 40-nm CMOS Process. In IEEE International Conference on Integrated Circuits, Technologies and Applications, ICTA 2023, Hefei, China, October 27-29, 2023. pages 120-121, IEEE, 2023. [doi]

@inproceedings{WangZSZLWL23,
  title = {A 64-Gb/s 0.33-pJ/bit PAM4 Receiver Analog Front-End with a Single-Stage Triple-Peaking CTLE Achieving 22.5-dB Boost in 40-nm CMOS Process},
  author = {Guoqing Wang and Zhao Zhang 0004 and Xinyu Shen and Zhaoyu Zhang and Jian Liu 0021 and Nanjian Wu and Liyuan Liu},
  year = {2023},
  doi = {10.1109/ICTA60488.2023.10364305},
  url = {https://doi.org/10.1109/ICTA60488.2023.10364305},
  researchr = {https://researchr.org/publication/WangZSZLWL23},
  cites = {0},
  citedby = {0},
  pages = {120-121},
  booktitle = {IEEE International Conference on Integrated Circuits, Technologies and Applications, ICTA 2023, Hefei, China, October 27-29, 2023},
  publisher = {IEEE},
  isbn = {979-8-3503-4428-8},
}