A 64-Gb/s 0.33-pJ/bit PAM4 Receiver Analog Front-End with a Single-Stage Triple-Peaking CTLE Achieving 22.5-dB Boost in 40-nm CMOS Process

Guoqing Wang, Zhao Zhang 0004, Xinyu Shen, Zhaoyu Zhang, Jian Liu 0021, Nanjian Wu, Liyuan Liu. A 64-Gb/s 0.33-pJ/bit PAM4 Receiver Analog Front-End with a Single-Stage Triple-Peaking CTLE Achieving 22.5-dB Boost in 40-nm CMOS Process. In IEEE International Conference on Integrated Circuits, Technologies and Applications, ICTA 2023, Hefei, China, October 27-29, 2023. pages 120-121, IEEE, 2023. [doi]

Abstract

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