BIST Methodology, Architecture and Circuits for Pre-Bond TSV Testing in 3D Stacking IC Systems - researchr publication authors

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Chao Wang, Jun Zhou, Roshan Weerasekera, Bin Zhao, Xin Liu, Philippe Royannez, Minkyu Je. BIST Methodology, Architecture and Circuits for Pre-Bond TSV Testing in 3D Stacking IC Systems. IEEE Trans. on Circuits and Systems, 62-I(1):139-148, 2015. [doi]

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