Chao Wang, Jun Zhou, Roshan Weerasekera, Bin Zhao, Xin Liu, Philippe Royannez, Minkyu Je. BIST Methodology, Architecture and Circuits for Pre-Bond TSV Testing in 3D Stacking IC Systems. IEEE Trans. on Circuits and Systems, 62-I(1):139-148, 2015. [doi]
@article{WangZWZLRJ15,
title = {BIST Methodology, Architecture and Circuits for Pre-Bond TSV Testing in 3D Stacking IC Systems},
author = {Chao Wang and Jun Zhou and Roshan Weerasekera and Bin Zhao and Xin Liu and Philippe Royannez and Minkyu Je},
year = {2015},
doi = {10.1109/TCSI.2014.2354752},
url = {http://dx.doi.org/10.1109/TCSI.2014.2354752},
researchr = {https://researchr.org/publication/WangZWZLRJ15},
cites = {0},
citedby = {0},
journal = {IEEE Trans. on Circuits and Systems},
volume = {62-I},
number = {1},
pages = {139-148},
}