Scalable counter architecture for a pre-loadable 1 GHz@0.6 um/5V pre-scaler in TSPC

Andreas Wassatsch, Dirk Timmermann. Scalable counter architecture for a pre-loadable 1 GHz@0.6 um/5V pre-scaler in TSPC. In International Symposium on Circuits and Systems (ISCAS 2001), 6-9 May 2001, Sydney, Australia. pages 92-95, IEEE, 2001. [doi]

Abstract

Abstract is missing.