Allen Waters, Un-Ku Moon. A fully automated verilog-to-layout synthesized ADC demonstrating 56dB-SNDR with 2MHz-BW. In IEEE Asian Solid-State Circuits Conference, A-SSCC 2015, Xia'men, China, November 9-11, 2015. pages 1-4, IEEE, 2015. [doi]
@inproceedings{WatersM15,
title = {A fully automated verilog-to-layout synthesized ADC demonstrating 56dB-SNDR with 2MHz-BW},
author = {Allen Waters and Un-Ku Moon},
year = {2015},
doi = {10.1109/ASSCC.2015.7387508},
url = {http://dx.doi.org/10.1109/ASSCC.2015.7387508},
researchr = {https://researchr.org/publication/WatersM15},
cites = {0},
citedby = {0},
pages = {1-4},
booktitle = {IEEE Asian Solid-State Circuits Conference, A-SSCC 2015, Xia'men, China, November 9-11, 2015},
publisher = {IEEE},
isbn = {978-1-4673-7191-9},
}