Compact modelling of Through-Silicon Vias (TSVs) in three-dimensional (3-D) integrated circuits - researchr publication authors

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Roshan Weerasekera, Matt Grange, Dinesh Pamunuwa, Hannu Tenhunen, Li-Rong Zheng. Compact modelling of Through-Silicon Vias (TSVs) in three-dimensional (3-D) integrated circuits. In IEEE International Conference on 3D System Integration, 3DIC 2009, San Francisco, California, USA, 28-30 September 2009. pages 1-8, IEEE, 2009. [doi]

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