Abstract is missing.
- Ultralow impedance evaluation system of wideband frequency for power distribution network of decoupling capacitor embedded substratesKatsuya Kikuchi, Koichi Takemura, Chihiro Ueda, Osamu Shimada, Toshio Gomyo, Yukiharu Takeuchi, Toshikazu Okubo, Kazuhiro Baba, Masahiro Aoyagi, Toshio Sudo, Kanji Otsuka. 1-4 [doi]
- Miniature wireless activity monitor using 3D system integrationRic van Doremalen, Piet van Engen, Wouter Jochems, Shi Cheng, Thomas Fritzsch, Walter De Raedt. 1-7 [doi]
- Low Cost of Ownership scalable copper Direct Bond Interconnect 3D IC technology for three dimensional integrated circuit applicationsPaul Enquist, G. Fountain, C. Petteway, A. Hollingsworth, H. Grady. 1-6 [doi]
- Advanced 3D chip stack process for thin dies with fine pitch bumps using pre-applied inter chip fillAkihiro Horibe, Fumiaki Yamada. 1-4 [doi]
- Effect of resistance of TSV s on performance of boost converter for low power 3D SSD with NAND flash memoriesTadashi Yasufuku, Koichi Ishida, Shinji Miyamoto, Hiroto Nakai, Makoto Takamiya, Takayasu Sakurai, Ken Takeuchi. 1-4 [doi]
- Impact of parameter accuracy on 3D designAdam Beece, Kenneth Rose, Tong Zhang, Jiang-Qian Lu. 1-7 [doi]
- 10 µm fine pitch Cu/Sn micro-bumps for 3-D super-chip stackYuki Ohara, Akihiro Noriki, Katsuyuki Sakuma, Kang-Wook Lee, Mariappan Murugesan, Jichoel Bea, Fumiaki Yamada, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi. 1-6 [doi]
- Thermal resistance measurements of interconnections for a three-dimensional (3D) chip stackKeiji Matsumoto, Soichiro Ibaraki, Katsuyuki Sakuma, Fumiaki Yamada. 1-5 [doi]
- Die stacking using 3D-wafer level packaging copper/polymer through-si via technology and Cu/Sn interconnect bumpingYann Civale, Deniz Sabuncuoglu Tezcan, Harold G. G. Philipsen, P. Jaenen, R. Agarwal, F. Duval, Philippe Soussan, Youssef Travaly, Eric Beyne. 1-4 [doi]
- A routerless system level interconnection network for 3D integrated systemsKelli Ireland, Donald M. Chiarulli, Steven P. Levitan. 1-6 [doi]
- Aluminum-Germanium eutectic bonding for 3D integrationF. Crnogorac, R. Birringer, R. Dauskardt, F. Pease. 1-5 [doi]
- System-level comparison of power delivery design for 2D and 3D ICsNauman H. Khan, Syed M. Alam, Soha Hassoun. 1-7 [doi]
- Development of wafer thinning and dicing technology for thin waferChuichi Miyazaki, Haruo Shimamoto, Toshihide Uematsu, Yoshiyuki Abe. 1-4 [doi]
- 3D interconnects for dense die stack packagesLaura Mirkarimi, M. Huynh, Piyush Savalia, Vage Oganesian. 1-5 [doi]
- Chip-to-chip communication based on capacitive couplingR. Cardu, Mauro Scandiuzzo, S. Cani, L. Perugini, Eleonora Franchi, Roberto Canegallo, Roberto Guerrieri. 1-6 [doi]
- A parallel ADC for high-speed CMOS image processing system with 3D structureKouji Kiyoyama, Yuki Ohara, Kang-Wook Lee, Y. Yang, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi. 1-4 [doi]
- 3-D memory organization and performance analysis for multi-processor network-on-chip architectureAwet Yemane Weldezion, Zhonghai Lu, Roshan Weerasekera, Hannu Tenhunen. 1-7 [doi]
- 3D integration technology for set-top box applicationDavid Henry, Séverine Cheramy, Jean Charbonnier, Pascal Chausse, Muriel Neyret, Cathy Brunet-Manquat, Sophie Verrun, Nicolas Sillon, Laurent Bonnot, Xavier Gagnard, E. Saugier. 1-7 [doi]
- Modelling of Through Silicon Via RF performance and impact on signal transmission in 3D integrated circuitsLionel Cadix, Alexis Farcy, Cédric Bermond, Christine Fuchs, Patrick Leduc, Maxime Rousseau, Myriam Assous, Alexandre Valentian, Julie Roullard, Elie Eid, Nicolas Sillon, Bernard Fléchet, Pascal Ancey. 1-7 [doi]
- Evaluation of fine grain 3-D integrated arithmetic unitsRyusuke Egawa, Jubee Taday, Hiroaki Kobayashi, Gensuke Gotoy. 1-8 [doi]
- Technology impact analysis for 3D TCAMEun Chu Oh, Paul D. Franzon. 1-5 [doi]
- A route towards production-worthy 5 µm × 25 µm and 1 µm × 20 µm non-Bosch through-silicon-via (TSV) etch, TSV metrology, and TSV integrationWeng Hong Teh, Raymond Caramto, Jamal Qureshi, Sitaram Arkalgud, M. O Brien, T. Gilday, Kou Maekawa, T. Saito, Kouichi Maruyama, Thenappan Chidambaram, Wei Wang, David Marx, D. Grant, Russ Dudley. 1-5 [doi]
- SrTiO3 thin film decoupling capacitors on Si interposers for 3D system integrationKoichi Takemura, Katsuya Kikuchi, Chihiro Ueda, Kazuhiro Baba, Masahiro Aoyagi, Kanji Otsuka. 1-5 [doi]
- Through Silicon Via(TSV) defect/pinhole self test circuit for 3D-ICMenglin Tsai, Amy Klooz, Alexander Leonard, Jennie Appel, Paul Franzon. 1-8 [doi]
- 3D TSV processes and its assembly/packaging technologySeung Wook Yoon, Dae Wook Yang, Jae Hoon Koo, Meenakshi Padmanathan, Flynn Carson. 1-5 [doi]
- 3D Stacked IC demonstrator using Hybrid Collective Die-to-Wafer bonding with copper Through Silicon Vias (TSV)Jan Van Olmen, Jan Coenen, Wim Dehaene, Kristin De Meyer, Cedric Huyghebaert, Anne Jourdain, Guruprasad Katti, Abdelkarim Mercha, Micha Rakowski, Michele Stucchi, Youssef Travaly, Eric Beyne, Bart Swinnen. 1-5 [doi]
- Junction-level thermal extraction and simulation of 3DICsSamson Melamed, Thorlindur Thorolfsson, Adi Srinivasan, Edmund Cheng, Paul Franzon, Rhett Davis. 1-7 [doi]
- First integration of Cu TSV using die-to-wafer direct bonding and planarizationPatrick Leduc, Myriam Assous, Léa Di Cioccio, Marc Zussy, Thomas Signamarcheix, Antonio Roman, Maxime Rousseau, Sophie Verrun, Laurent Bally, David Bouchu, Lionel Cadix, Alexis Farcy, Nicolas Sillon. 1-5 [doi]
- Material improvement for ultrathin-wafer handling in TSV creation and PECVD processAmadine Jouve, Wenbin Hong, D. Blumenshine, JoElle Dachsteiner, Rama Puligadda, Dongshun Bai, J. Diaz, David Henry. 1-5 [doi]
- Thermal analysis for a SiGe HBT 40 watt 32 GHz clock 3D memory processor chip stack using diamond heat spreader layersJohn F. McDonald, Okan Erdogan, Philip Jacob, Paul M. Belemjian, Alexey Gutin, Aamir Zia, Michael Chu, Jin-Woo Kim, Ryan Clarke, Nate DeSimone, Sherry Liu, Russell P. Kraft. 1-7 [doi]
- Through-Silicon Via (TSV)-induced noise characterization and noise mitigation using coaxial TSVsNauman H. Khan, Syed M. Alam, Soha Hassoun. 1-7 [doi]
- Comparative analysis of two 3D integration implementations of a SAR processorThorlindur Thorolfsson, Samson Melamed, Gary Charles, Paul D. Franzon. 1-4 [doi]
- Reliability aspects of 3D-oriented heterogeneous device design related to stress sensitivity of MOS transistorsGrzegorz Janczyk, Tomasz Bieniek, J. Szynka, P. Grabiec. 1-6 [doi]
- Developments of novel vertically integrated pixel sensors in the high energy physics communityMarcel Demarteau, Yasuo Arai, Hans-Günther Moser, Valerio Re. 1-7 [doi]
- Validation of the porous-medium approach to model interlayer-cooled 3D-chip stacksThomas Brunschwiler, Stephan Paredes, Ute Drechsler, Bruno Michel, W. Cesar, G. Toral, Yuksel Temiz, Yusuf Leblebici. 1-10 [doi]
- Predictive High Frequency effects of substrate coupling in 3D integrated circuits stackingElie Eid, Thierry Lacrevaz, Sébastien de Rivaz, Cédric Bermond, Bernard Fléchet, Francis Calmon, Christian Gontrand, Alexis Farcy, Lionel Cadix, Pascal Ancey. 1-6 [doi]
- Fabrication and packaging of microbump interconnections for 3D TSVSeung Wook Yoon, Jae Hoon Ku, Nathapong Suthiwongsunthorn, Pandi Chelvam Marimuthu, Flynn Carson. 1-5 [doi]
- A review of wafer bonding materials and characterizations to enable wafer thinning, backside processing, and laser dicingG. Williams, Patrick O Hara, J. Moore, B. Gordon, J. Rose. 1 [doi]
- Design tools for the 3D roadmapLisa D. McIlrath, Wahid Ahmed, Andrew Yip. 1-4 [doi]
- Achieving low temperature Cu to Cu diffusion bonding with self assembly monolayer (SAM) passivationDau Fatt Lim, Shiv Govind Singh, Xiao Fang Ang, Jun Wei, Chee Mang Ng, Chuan Seng Tan. 1-5 [doi]
- Thermotropic liquid crystalline polyimides toward high heat conducting materials for 3D chip stackTomohide Murase, Hiroyuki Aikyou, Fumikazu Mizutani, Yu Shoji, Tomoya Higashihara, Mitsuru Ueda. 1-4 [doi]
- High speed I/O and thermal effect characterization of 3D stacked ICsMoishe Groger, Shadi M. Harb, Devin Morris, William R. Eisenstadt, Sudeep Puligundla. 1-5 [doi]
- Thin wafer handling - Study of temporary wafer bonding materials and processesJames Hermanowski. 1-5 [doi]
- Wafer-scale 3D integration of InGaAs image sensors with Si readout circuitsChang-Lee Chen, D.-R. Yost, Jeffrey M. Knecht, David C. Chapman, Douglas C. Oakley, Leonard J. Mahoney, Joseph P. Donnelly, Antonio M. Soares, Vyshnavi Suntharalingam, Robert Berger, V. Bolkhovsky, W. Hu, Bruce D. Wheeler, Craig L. Keast, David C. Shaver. 1-4 [doi]
- 3D on-chip memory for the vector architectureYusuke Funaya, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi. 1-6 [doi]
- Wet-process deposition of TSV liner and metal filmsClaudio Truzzi, Frédéric Raynal, Vincent Mevellec. 1-6 [doi]
- An innovative die to wafer 3D integration scheme: Die to wafer oxide or copper direct bonding with planarised oxide inter-die fillingLéa Di Cioccio, Pierric Gueguen, Rachid Taibi, Thomas Signamarcheix, Laurent Bally, Laurent Vandroux, Marc Zussy, Sophie Verrun, Jérôme Dechamp, Patrick Leduc, Myriam Assous, David Bouchu, François de Crecy, Laurent-Luc Chapelon, Laurent Clavelier. 1-4 [doi]
- 3-D thin chip integration technology - from technology development to applicationThomas Fritzsch, Raul Mrossko, Tobias Baumgartner, Michael Toepper, Matthias Klein, Jürgen Wolf, Bernhard Wunderle, Herbert Reichl. 1-8 [doi]
- Compact modelling of Through-Silicon Vias (TSVs) in three-dimensional (3-D) integrated circuitsRoshan Weerasekera, Matt Grange, Dinesh Pamunuwa, Hannu Tenhunen, Li-Rong Zheng. 1-8 [doi]
- Evaluation of energy-recovering interconnects for low-power 3D stacked ICsPanagiotis Asimakopoulos, Geert Van der Plas, Alex Yakovlev, Paul Marchal. 1-5 [doi]
- Modeling and evaluation for electrical characteristics of through-strata-vias (TSVS) in three-dimensional integrationZheng Xu, Adam Beece, Kenneth Rose, Tong Zhang, Jian-Qiang Lu. 1-9 [doi]
- Development of feed-forward design system for rapid SiP designTomokatsu Mizukusa, Tamio Nagano, Yasuo Shimizu, Kazuyuki Sakata, Kazuo Kato. 1-4 [doi]
- IC-package co-design and analysis for 3D-IC designsThomas Whipple, Taranjit Kukal, Keith Felton, Vassilios Gerousis. 1-6 [doi]
- Etch, dielectrics and metal barrier-seed for low temperature through-silicon via processingKeith Buchanan, Stephen Burgess, Kathrine Giles, Matthew Muggeridge, Hao Zhao. 1-4 [doi]
- Architectural evaluation of 3D stacked RRAM cachesDean L. Lewis, HsienHsin S. Lee. 1-4 [doi]
- Influence of 3D integration on 2D interconnections and 2D self inductors HF propertiesJulie Roullard, Stéphane Capraro, Thierry Lacrevaz, Lionel Cadix, Elie Eid, Alexis Farcy, Bernard Fléchet. 1-6 [doi]
- Delay analysis and design exploration for 3D SRAMXi Chen, William Rhett Davis. 1-4 [doi]
- Impact of 3D design choices on manufacturing costDimitrios Velenis, Michele Stucchi, Erik Jan Marinissen, Bart Swinnen, Eric Beyne. 1-5 [doi]
- 3D integrated circuits for lab-on-chip applicationsSamuel J. Dickerson, Steven P. Levitan, Donald M. Chiarulli. 1-8 [doi]
- Investigation and comparison of thermal distribution in synchronous and asynchronous 3D ICsBrent Hollosi, Tao Zhang, Ravi Sankar Parameswaran Nair, Yuan Xie, Jia Di, Scott Smith. 1-5 [doi]
- Wafer Thickness Sensor (WTS) for etch depth measurement of TSVDavid Marx, David Grant, Russ Dudley, Andy Rudack, W. H. Teh. 1-5 [doi]
- Impact of thermal through silicon via (TTSV) on the temperature profile of multi-layer 3-D device stackShiv Govind Singh, Chuan Seng Tan. 1-4 [doi]
- A capacitive coupling interface with high sensitivity for wireless wafer testingGil-Su Kim, Makoto Takamiya, Takayasu Sakurai. 1-5 [doi]
- Advanced wafer bonding solutions for TSV integration with thin wafersBioh Kim, Thorsten Matthias, Markus Wimplinger, Paul Lindner. 1-6 [doi]
- Heterogeneous integration technology for MEMS-LSI multi-chip moduleKang-Wook Lee, Shigeyuki Kanno, Yuki Ohara, Kouji Kiyoyama, Ji Chel Bea, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi. 1-6 [doi]
- The benefits of 3D networks-on-chip as shown with LDPC decodingChristopher Mineo, William Rhett Davis. 1-8 [doi]
- Arithmetic unit design using 180nm TSV-based 3D stacking technologyJin Ouyang, Guangyu Sun, Yibo Chen, Lian Duan, Tao Zhang, Yuan Xie, Mary Jane Irwin. 1-4 [doi]
- Automated Pathfinding tool chain for 3D-stacked integrated circuits: Practical case studyDragomir Milojevic, Trevor Carlson, Kris Croes, Riko Radojcic, Diana F. Ragett, Dirk Seynhaeve, Federico Angiolini, Geert Van der Plas, Paul Marchal. 1-6 [doi]
- 3D integration technology for 3D stacked retinal chipYoshiyuki Kaiho, Yuki Ohara, Hirotaka Takeshita, Kouji Kiyoyama, Kang-Wook Lee, Tetsu Tanaka, Mitsumasa Koyanagi. 1-4 [doi]
- Robust verification of 3D-ICs: Pros, cons and recommendationsMatthew Hogan, Dusan Petranovic. 1-6 [doi]
- Micro-Raman spectroscopy analysis and capacitance - time (C-t) measurement of thinned silicon substrates for 3D integrationJi Chel Bea, Mariappan Murugesan, Yuki Ohara, Akihiro Noriki, Hisaski Kino, Kang-Wook Lee, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi. 1-5 [doi]
- Electrical modeling of Through Silicon and Package ViasTapobrata Bandyopadhyay, Ritwik Chatterjee, Daehyun Chung, Madhavan Swaminathan, Rao Tummala. 1-8 [doi]
- A tileable switch module architecture for homogeneous 3D FPGAsSeyyed Ahmad Razavi, Morteza Saheb Zamani, Kia Bazargan. 1-4 [doi]
- Electrical-thermal co-analysis for power delivery networks in 3D system integrationJianyong Xie, Daehyun Chung, Madhavan Swaminathan, Michael McAllister, Alina Deutsch, Lijun Jiang, Barry J. Rubin. 1-4 [doi]
- Physical mapping and performance study of a multi-clock 3-Dimensional Network-on-Chip meshMatt Grange, Awet Yemane Weldezion, Dinesh Pamunuwa, Roshan Weerasekera, Zhonghai Lu, Axel Jantsch, Dave Shippen. 1-7 [doi]
- Impacts of though-DRAM vias in 3D processor-DRAM integrated systemsQi Wu, Kenneth Rose, Jian-Qiang Lu, Tong Zhang. 1-6 [doi]
- 3D optical networks-on-chip (NoC) for multiprocessor systems-on-chip (MPSoC)Yaoyao Ye, Lian Duan, Jiang Xu, Jin Ouyang, Mo Kwai Hung, Yuan Xie. 1-6 [doi]
- TSV metrology and inspection challengesRamakanth Alapati, Youssef Travaly, Jan Van Olmen, Ricardo Cotrin Teixeira, Jan Vaes, Marc van Cauwenbergh, Anne Jourdain, Greet Verbinnen, Gino Marcuccilli, Glenn Florence, Shay Wolfling, Christine Pelissier, Haiping Zhang, Jaydeep Sinha, Andreas Machura, Irfan Malik. 1-4 [doi]
- Development of Functionally innovative 3D-Integrated Circuit (Dream Chip) technology / High-Density 3D-Integration Technology for Multifunctional DevicesMorihiro Kada. 1-6 [doi]
- Development of a new self-assembled die bonder to three-dimensionally stack known good dies in batchTakafumi Fukushima, Eiji Iwata, Tetsu Tanaka, Mitsumasa Koyanagi. 1-4 [doi]