Arnold Weinberger, Jay L. Smith. The logical design of a 1-microsecond parallel adder using 1-megacycle circuitry. In Oliver Whitby, editor, Papers presented at the 1956 joint ACM-AIEE-IRE western computer conference, AIEE-IRE 1956 (Western), San Francisco, California, USA, February 7-9, 1956. pages 103-108, ACM, 1956. [doi]
@inproceedings{WeinbergerS56-0,
title = {The logical design of a 1-microsecond parallel adder using 1-megacycle circuitry},
author = {Arnold Weinberger and Jay L. Smith},
year = {1956},
doi = {10.1145/1455410.1455450},
url = {https://doi.org/10.1145/1455410.1455450},
researchr = {https://researchr.org/publication/WeinbergerS56-0},
cites = {0},
citedby = {0},
pages = {103-108},
booktitle = {Papers presented at the 1956 joint ACM-AIEE-IRE western computer conference, AIEE-IRE 1956 (Western), San Francisco, California, USA, February 7-9, 1956},
editor = {Oliver Whitby},
publisher = {ACM},
isbn = {978-1-4503-7858-1},
}