The logical design of a 1-microsecond parallel adder using 1-megacycle circuitry

Arnold Weinberger, Jay L. Smith. The logical design of a 1-microsecond parallel adder using 1-megacycle circuitry. In Oliver Whitby, editor, Papers presented at the 1956 joint ACM-AIEE-IRE western computer conference, AIEE-IRE 1956 (Western), San Francisco, California, USA, February 7-9, 1956. pages 103-108, ACM, 1956. [doi]

Abstract

Abstract is missing.