Tai-Hao Wen, Hung-Hsi Hsu, Win-San Khwa, Wei-Hsing Huang, Zhao-En Ke, Yu-Hsiang Chin, Hua-Jin Wen, Yu-Chen Chang, Wei-Ting Hsu, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Shih-Hsih Teng, Chung-Cheng Chou, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang. 34.8 A 22nm 16Mb Floating-Point ReRAM Compute-in-Memory Macro with 31.2TFLOPS/W for AI Edge Devices. In IEEE International Solid-State Circuits Conference, ISSCC 2024, San Francisco, CA, USA, February 18-22, 2024. pages 580-582, IEEE, 2024. [doi]
@inproceedings{WenHKHKCWCHLLHTTCCCC24,
title = {34.8 A 22nm 16Mb Floating-Point ReRAM Compute-in-Memory Macro with 31.2TFLOPS/W for AI Edge Devices},
author = {Tai-Hao Wen and Hung-Hsi Hsu and Win-San Khwa and Wei-Hsing Huang and Zhao-En Ke and Yu-Hsiang Chin and Hua-Jin Wen and Yu-Chen Chang and Wei-Ting Hsu and Chung-Chuan Lo and Ren-Shuo Liu and Chih-Cheng Hsieh and Kea-Tiong Tang and Shih-Hsih Teng and Chung-Cheng Chou and Yu-Der Chih and Tsung-Yung Jonathan Chang and Meng-Fan Chang},
year = {2024},
doi = {10.1109/ISSCC49657.2024.10454468},
url = {https://doi.org/10.1109/ISSCC49657.2024.10454468},
researchr = {https://researchr.org/publication/WenHKHKCWCHLLHTTCCCC24},
cites = {0},
citedby = {0},
pages = {580-582},
booktitle = {IEEE International Solid-State Circuits Conference, ISSCC 2024, San Francisco, CA, USA, February 18-22, 2024},
publisher = {IEEE},
isbn = {979-8-3503-0620-0},
}