Timing Optimization in Sequential Circuit by Exploiting Clock-Gating Logic

Shih-Hung Weng, Yu-Min Kuo, Shih-Chieh Chang. Timing Optimization in Sequential Circuit by Exploiting Clock-Gating Logic. ACM Trans. Design Autom. Electr. Syst., 17(2):16, 2012. [doi]

Authors

Shih-Hung Weng

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Yu-Min Kuo

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Shih-Chieh Chang

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