An Asynchronous Superscalar Architecture for Exploiting Instruction-Level Parallelism

Tony Werner, Venkatesh Akella. An Asynchronous Superscalar Architecture for Exploiting Instruction-Level Parallelism. In 7th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2001), 11-14 March 2001, Salt Lake City, UT, USA. pages 140-151, IEEE Computer Society, 2001. [doi]

@inproceedings{WernerA01,
  title = {An Asynchronous Superscalar Architecture for Exploiting Instruction-Level Parallelism},
  author = {Tony Werner and Venkatesh Akella},
  year = {2001},
  url = {http://csdl.computer.org/comp/proceedings/async/2001/1034/00/10340140abs.htm},
  tags = {architecture},
  researchr = {https://researchr.org/publication/WernerA01},
  cites = {0},
  citedby = {0},
  pages = {140-151},
  booktitle = {7th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2001), 11-14 March 2001, Salt Lake City, UT, USA},
  publisher = {IEEE Computer Society},
  isbn = {0-7695-1034-5},
}