Designing Low-Power, Low-Latency Networks-on-Chip by Optimally Combining Electrical and Optical Links

Sebastian Werner, Javier Navaridas, Mikel Luján. Designing Low-Power, Low-Latency Networks-on-Chip by Optimally Combining Electrical and Optical Links. In 2017 IEEE International Symposium on High Performance Computer Architecture, HPCA 2017, Austin, TX, USA, February 4-8, 2017. pages 265-276, IEEE Computer Society, 2017. [doi]

@inproceedings{WernerNL17,
  title = {Designing Low-Power, Low-Latency Networks-on-Chip by Optimally Combining Electrical and Optical Links},
  author = {Sebastian Werner and Javier Navaridas and Mikel Luján},
  year = {2017},
  doi = {10.1109/HPCA.2017.23},
  url = {https://doi.org/10.1109/HPCA.2017.23},
  researchr = {https://researchr.org/publication/WernerNL17},
  cites = {0},
  citedby = {0},
  pages = {265-276},
  booktitle = {2017 IEEE International Symposium on High Performance Computer Architecture, HPCA 2017, Austin, TX, USA, February 4-8, 2017},
  publisher = {IEEE Computer Society},
  isbn = {978-1-5090-4985-1},
}