Abstract is missing.
- Towards Pervasive and User Satisfactory CNN across GPU MicroarchitecturesMingcong Song, Yang Hu, Huixiang Chen, Tao Li. 1-12 [doi]
- Near-Optimal Access Partitioning for Memory Hierarchies with Multiple Heterogeneous Bandwidth SourcesJayesh Gaur, Mainak Chaudhuri, Pradeep Ramachandran, Sreenivas Subramoney. 13-24 [doi]
- NCAP: Network-Driven, Packet Context-Aware Power Management for Client-Server ArchitectureMohammad Alian, Ahmed H. M. O. Abulila, Lokesh Jindal, Daehoon Kim, Nam Sung Kim. 25-36 [doi]
- Supporting Address Translation for Accelerator-Centric ArchitecturesYuchen Hao, Zhenman Fang, Glenn Reinman, Jason Cong. 37-48 [doi]
- Vulnerabilities in MLC NAND Flash Memory Programming: Experimental Analysis, Exploits, and Mitigation TechniquesYu Cai, Saugata Ghose, Yixin Luo, Ken Mai, Onur Mutlu, Erich F. Haratsch. 49-60 [doi]
- Defect Analysis and Cost-Effective Resilience Architecture for Future DRAM DevicesSang-uhn Cha, Seongil O, Hyunsung Shin, Sangjoon Hwang, Kwang-Il Park, Seong-Jin Jang, Joo-Sun Choi, Gyo-Young Jin, Young Hoon Son, Hyunyoon Cho, Jung Ho Ahn, Nam Sung Kim. 61-72 [doi]
- Architecting an Energy-Efficient DRAM System for GPUsNiladrish Chatterjee, Mike O'Connor, Donghyuk Lee, Daniel R. Johnson, Stephen W. Keckler, Minsoo Rhu, William J. Dally. 73-84 [doi]
- Design and Analysis of an APU for Exascale ComputingThiruvengadam Vijayaraghavan, Yasuko Eckert, Gabriel H. Loh, Michael J. Schulte, Mike Ignatowski, Bradford M. Beckmann, William C. Brantley, Joseph L. Greathouse, Wei Huang, Arun Karunanithi, Onur Kayiran, Mitesh R. Meswani, Indrani Paul, Matthew Poremba, Steven Raasch, Steven K. Reinhardt, Greg Sadowski, Vilas Sridharan. 85-96 [doi]
- BRAVO: Balanced Reliability-Aware Voltage OptimizationKarthik Swaminathan, Nandhini Chandramoorthy, Chen-Yong Cher, Ramon Bertran, Alper Buyuktosunoglu, Pradip Bose. 97-108 [doi]
- Maximizing Cache Performance Under UncertaintyNathan Beckmann, Daniel Sanchez. 109-120 [doi]
- SWAP: Effective Fine-Grain Management of Shared Last-Level Caches with Minimum Hardware SupportXiaodong Wang, Shuang Chen, Jeff Setter, José F. Martínez. 121-132 [doi]
- A Split Cache Hierarchy for Enabling Data-Oriented OptimizationsAndreas Sembrant, Erik Hagersten, David Black-Schaffer. 133-144 [doi]
- Fast and Accurate Exploration of Multi-level Caches Using Hierarchical Reuse DistanceRafael K. V. Maeda, Qiong Cai, Jiang Xu, Zhe Wang, Zhongyuan Tian. 145-156 [doi]
- Enabling Effective Module-Oblivious Power Gating for Embedded ProcessorsHari Cherupalli, Henry Duwe, Weidong Ye, Rakesh Kumar 0002, John Sartori. 157-168 [doi]
- Application-Specific Performance-Aware Energy Optimization on Android Mobile DevicesKarthik Rao, Jun Wang, Sudhakar Yalamanchili, Yorai Wardi, Handong Ye. 169-180 [doi]
- Fast Decentralized Power Capping for Server ClustersReza Azimi, Masoud Badiei, Xin Zhan, Na Li, Sherief Reda. 181-192 [doi]
- Random Folded Clos Topologies for Datacenter NetworksCristobal Camarero, Carmen Martínez, Ramón Beivide. 193-204 [doi]
- Tiny Directory: Efficient Shared Memory in Many-Core Systems with Ultra-Low-Overhead Coherence TrackingSudhanshu Shukla, Mainak Chaudhuri. 205-216 [doi]
- Partial Row Activation for Low-Power DRAM SystemYebin Lee, Hyeonggyu Kim, Seokin Hong, Soontae Kim. 217-228 [doi]
- Understanding and Optimizing Power Consumption in Memory NetworksXun Jian, Pavan Kumar Hanumolu, Rakesh Kumar 0002. 229-240 [doi]
- SoftMC: A Flexible and Practical Open-Source Infrastructure for Enabling Experimental DRAM StudiesHasan Hassan, Nandita Vijaykumar, Samira Manabi Khan, Saugata Ghose, Kevin K. Chang, Gennady Pekhimenko, Donghyuk Lee, Oguz Ergin, Onur Mutlu. 241-252 [doi]
- Static Bubble: A Framework for Deadlock-Free Irregular On-chip TopologiesAniruddh Ramrakhyani, Tushar Krishna. 253-264 [doi]
- Designing Low-Power, Low-Latency Networks-on-Chip by Optimally Combining Electrical and Optical LinksSebastian Werner, Javier Navaridas, Mikel Luján. 265-276 [doi]
- Near-Ideal Networks-on-Chip for ServersPejman Lotfi-Kamran, Mehdi Modarressi, Hamid Sarbazi-Azad. 277-288 [doi]
- Design and Evaluation of AWGR-Based Photonic NoC Architectures for 2.5D Integrated High Performance Computing SystemsPaolo Grani, Roberto Proietti, Venkatesh Akella, S. J. Ben Yoo. 289-300 [doi]
- Secure Dynamic Memory Scheduling Against Timing Channel AttacksYao Wang, Benjamin Wu, G. Edward Suh. 301-312 [doi]
- Cold Boot Attacks are Still Hot: Security Analysis of Memory Scramblers in Modern ProcessorsSalessawi Ferede Yitbarek, Misiker Tadesse Aga, Reetuparna Das, Todd M. Austin. 313-324 [doi]
- Cooperative Path-ORAM for Effective Memory Bandwidth Sharing in Server SettingsRujia Wang, Youtao Zhang, Jun Yang 0002. 325-336 [doi]
- Camouflage: Memory Traffic Shaping to Mitigate Timing AttacksYanqi Zhou, Sameer Wagh, Prateek Mittal, David Wentzlaff. 337-348 [doi]
- SILC-FM: Subblocked InterLeaved Cache-Like Flat Memory OrganizationJee Ho Ryoo, Mitesh R. Meswani, Andreas Prodromou, Lizy K. John. 349-360 [doi]
- ATOM: Atomic Durability in Non-volatile Memory through Hardware LoggingArpit Joshi, Vijay Nagarajan, Stratis Viglas, Marcelo Cintra. 361-372 [doi]
- KAML: A Flexible, High-Performance Key-Value SSDYanqin Jin, Hung-Wei Tseng, Yannis Papakonstantinou, Steven Swanson. 373-384 [doi]
- Balancing Performance and Lifetime of MLC PCM by Using a Region Retention MonitorMingzhe Zhang, Lunkai Zhang, Lei Jiang, Zhiyong Liu, Frederic T. Chong. 385-396 [doi]
- Reliability-Aware Scheduling on Heterogeneous Multicore ProcessorsAjeya Naithani, Stijn Eyerman, Lieven Eeckhout. 397-408 [doi]
- Hipster: Hybrid Task Manager for Latency-Critical Cloud WorkloadsRajiv Nishtala, Paul M. Carpenter, Vinicius Petrucci, Xavier Martorell. 409-420 [doi]
- Cooper: Task Colocation with Cooperative GamesQiuyun Llull, Songchun Fan, Seyed Majid Zahedi, Benjamin C. Lee. 421-432 [doi]
- MemPod: A Clustered Architecture for Efficient and Scalable Migration in Flat Address Space Multi-level MemoriesAndreas Prodromou, Mitesh R. Meswani, Nuwan Jayasena, Gabriel H. Loh, Dean M. Tullsen. 433-444 [doi]
- Exploring Hyperdimensional Associative MemoryMohsen Imani, Abbas Rahimi, Deqian Kong, Tajana Rosing, Jan M. Rabaey. 445-456 [doi]
- GraphPIM: Enabling Instruction-Level PIM Offloading in Graph Computing FrameworksLifeng Nai, Ramyad Hadidi, Jaewoong Sim, Hyojong Kim, Pranith Kumar, Hyesoon Kim. 457-468 [doi]
- High-Bandwidth Low-Latency Approximate Interconnection NetworksDaichi Fujiki, Kiyo Ishii, Ikki Fujiwara, Hiroki Matsutani, Hideharu Amano, Henri Casanova, Michihiro Koibuchi. 469-480 [doi]
- Compute CachesShaizeen Aga, Supreet Jeloka, Arun Subramaniyan 0001, Satish Narayanasamy, David Blaauw, Reetuparna Das. 481-492 [doi]
- Boomerang: A Metadata-Free Architecture for Control Flow DeliveryRakesh Kumar 0003, Cheng-Chieh Huang, Boris Grot, Vijay Nagarajan. 493-504 [doi]
- PABST: Proportionally Allocated Bandwidth at the Source and TargetDerek R. Hower, Harold W. Cain, Carl A. Waldspurger. 505-516 [doi]
- SOUP-N-SALAD: Allocation-Oblivious Access Latency Reduction with Asymmetric DRAM MicroarchitecturesYuhwan Ro, Hyunyoon Cho, Eojin Lee, Daejin Jung, Young Hoon Son, Jung Ho Ahn, Jae W. Lee. 517-528 [doi]
- Transparent and Efficient CFI Enforcement with Intel Processor TraceYutao Liu, Peitao Shi, Xinran Wang, Haibo Chen, Binyu Zang, Haibing Guan. 529-540 [doi]
- PipeLayer: A Pipelined ReRAM-Based Accelerator for Deep LearningLinghao Song, Xuehai Qian, Hai Li 0001, Yiran Chen. 541-552 [doi]
- FlexFlow: A Flexible Dataflow Accelerator Architecture for Convolutional Neural NetworksWenyan Lu, Guihai Yan, Jiajun Li, Shijun Gong, Yinhe Han, Xiaowei Li 0001. 553-564 [doi]
- Needle: Leveraging Program Analysis to Analyze and Extract Accelerators from Whole ProgramsSnehasish Kumar, Nick Sumner, Vijayalakshmi Srinivasan, Steve Margerm, Arrvindh Shriraman. 565-576 [doi]
- Radiation-Induced Error Criticality in Modern HPC Parallel AcceleratorsDaniel Alfonso Gonçalves de Oliveira, Laércio Lima Pilla, Mauricio Hanzich, Vinicius Fratin, Fernando Fernandes, Caio B. Lunardi, José María Cela, Philippe Olivier Alexandre Navaux, Luigi Carro, Paolo Rech. 577-588 [doi]
- Pilot Register File: Energy Efficient Partitioned Register File for GPUsMohammad Abdel-Majeed, Alireza Shafaei, Hyeran Jeon, Massoud Pedram, Murali Annavaram. 589-600 [doi]
- G-Scalar: Cost-Effective Generalized Scalar Execution Architecture for Power-Efficient GPUsZhenhong Liu, Syed Zohaib Gilani, Murali Annavaram, Nam Sung Kim. 601-612 [doi]
- Dynamic GPGPU Power Management Using Adaptive Model Predictive ControlAbhinandan Majumdar, Leonardo Piga, Indrani Paul, Joseph L. Greathouse, Wei Huang, David H. Albonesi. 613-624 [doi]
- Efficient Sequential Consistency in GPUs via Relativistic Cache CoherenceXiaowei Ren, Mieszko Lis. 625-636 [doi]
- Processing-in-Memory Enabled Graphics Processors for 3D RenderingChenhao Xie, Shuaiwen Leon Song, Jing Wang, Weigong Zhang, Xin Fu. 637-648 [doi]
- Controlled Kernel Launch for Dynamic Parallelism in GPUsXulong Tang, Ashutosh Pattnaik, Huaipan Jiang, Onur Kayiran, Adwait Jog, Sreepathi Pai, Mohamed Ibrahim, Mahmut T. Kandemir, Chita R. Das. 649-660 [doi]