Simulated evolutionary code generation for heterogeneous memory-register DSP-architectures

Bernhard Wess. Simulated evolutionary code generation for heterogeneous memory-register DSP-architectures. In 10th European Signal Processing Conference, EUSIPCO 2000, Tampere, Finland, September 4-8, 2000. pages 1-4, IEEE, 2000. [doi]

Abstract

Abstract is missing.