Chris Wilkerson, Alaa R. Alameldeen, Zeshan Chishti, Wei Wu, Dinesh Somasekhar, Shih-Lien Lu. Reducing cache power with low-cost, multi-bit error-correcting codes. In André Seznec, Uri Weiser, Ronny Ronen, editors, 37th International Symposium on Computer Architecture (ISCA 2010), June 19-23, 2010, Saint-Malo, France. pages 83-93, ACM, 2010. [doi]
@inproceedings{WilkersonACWSL10,
title = {Reducing cache power with low-cost, multi-bit error-correcting codes},
author = {Chris Wilkerson and Alaa R. Alameldeen and Zeshan Chishti and Wei Wu and Dinesh Somasekhar and Shih-Lien Lu},
year = {2010},
doi = {10.1145/1815961.1815973},
url = {http://doi.acm.org/10.1145/1815961.1815973},
tags = {caching},
researchr = {https://researchr.org/publication/WilkersonACWSL10},
cites = {0},
citedby = {0},
pages = {83-93},
booktitle = {37th International Symposium on Computer Architecture (ISCA 2010), June 19-23, 2010, Saint-Malo, France},
editor = {André Seznec and Uri Weiser and Ronny Ronen},
publisher = {ACM},
isbn = {978-1-4503-0053-7},
}