Chris Wilkerson, Alaa R. Alameldeen, Zeshan Chishti, Wei Wu, Dinesh Somasekhar, Shih-Lien Lu. Reducing cache power with low-cost, multi-bit error-correcting codes. In André Seznec, Uri Weiser, Ronny Ronen, editors, 37th International Symposium on Computer Architecture (ISCA 2010), June 19-23, 2010, Saint-Malo, France. pages 83-93, ACM, 2010. [doi]
Abstract is missing.