Cost-efficient Formal Block Verification for ASIC Design - researchr publication authors

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Klaus Winkelmann, Hans-Joachim Trylus, Dominik Stoffel, Görschwin Fey. Cost-efficient Formal Block Verification for ASIC Design. In Rolf Drechsler, editor, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Bremen, Germany, February 24-25, 2003. pages 184-188, Shaker, 2003.

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