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Low complexity VLSI implementation of a joint successive interference cancellation with interleaving scheme

Bob Ka-Man Wong, Chi-Ying Tsui, R. S.-K. Cheng. Low complexity VLSI implementation of a joint successive interference cancellation with interleaving scheme. In IEEE International Symposium on Circuits and Systems, ISCAS 2000, Emerging Technologies for the 21st Century, Geneva, Switzerland, 28-31 May 2000, Proceedings. pages 365-368, IEEE, 2000. [doi]

Authors

Bob Ka-Man Wong

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Chi-Ying Tsui

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R. S.-K. Cheng

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