David M. Wu. An optimized delay testing technique for LSSD-based VLSI logic circuits. In 9th IEEE VLSI Test Symposium (VTS'91), 15-17 Apr 1991, Atlantic City, NJ, USA. pages 239-248, IEEE, 1991. [doi]
@inproceedings{Wu91-1,
title = {An optimized delay testing technique for LSSD-based VLSI logic circuits},
author = {David M. Wu},
year = {1991},
doi = {10.1109/VTEST.1991.208165},
url = {http://dx.doi.org/10.1109/VTEST.1991.208165},
researchr = {https://researchr.org/publication/Wu91-1},
cites = {0},
citedby = {0},
pages = {239-248},
booktitle = {9th IEEE VLSI Test Symposium (VTS'91), 15-17 Apr 1991, Atlantic City, NJ, USA},
publisher = {IEEE},
}