An optimized delay testing technique for LSSD-based VLSI logic circuits

David M. Wu. An optimized delay testing technique for LSSD-based VLSI logic circuits. In 9th IEEE VLSI Test Symposium (VTS'91), 15-17 Apr 1991, Atlantic City, NJ, USA. pages 239-248, IEEE, 1991. [doi]

Abstract

Abstract is missing.