Low-latency Voltage-Racing Winner-Take-All (VR-WTA) circuit for acceleration of learning engine - researchr publication authors

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Chia-Heng Wu, Ting-Sheng Chen, Ding-Yuan Lee, Tsung-Te Liu, An-Yeu Wu. Low-latency Voltage-Racing Winner-Take-All (VR-WTA) circuit for acceleration of learning engine. In 2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017, Hsinchu, Taiwan, April 24-27, 2017. pages 1-4, IEEE, 2017. [doi]

This author has not been identified. Look up 'Chia-Heng Wu' in GoogleThis author has not been identified. Look up 'Ting-Sheng Chen' in GoogleThis author has not been identified. Look up 'Ding-Yuan Lee' in GoogleThis author has not been identified. Look up 'Tsung-Te Liu' in GoogleThis author has not been identified. Look up 'An-Yeu Wu' in Google

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