Chia-Heng Wu, Ting-Sheng Chen, Ding-Yuan Lee, Tsung-Te Liu, An-Yeu Wu. Low-latency Voltage-Racing Winner-Take-All (VR-WTA) circuit for acceleration of learning engine. In 2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017, Hsinchu, Taiwan, April 24-27, 2017. pages 1-4, IEEE, 2017. [doi]
@inproceedings{WuCLLW17,
title = {Low-latency Voltage-Racing Winner-Take-All (VR-WTA) circuit for acceleration of learning engine},
author = {Chia-Heng Wu and Ting-Sheng Chen and Ding-Yuan Lee and Tsung-Te Liu and An-Yeu Wu},
year = {2017},
doi = {10.1109/VLSI-DAT.2017.7939641},
url = {https://doi.org/10.1109/VLSI-DAT.2017.7939641},
researchr = {https://researchr.org/publication/WuCLLW17},
cites = {0},
citedby = {0},
pages = {1-4},
booktitle = {2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017, Hsinchu, Taiwan, April 24-27, 2017},
publisher = {IEEE},
isbn = {978-1-5090-3969-2},
}