A monolithic 1.25 Gbits/sec CMOS clock/data recovery circuit for fibre channel transceiver

L. Wu, H. Chen, S. Nagavarapu, Randall L. Geiger, E. Lee, W. Black. A monolithic 1.25 Gbits/sec CMOS clock/data recovery circuit for fibre channel transceiver. In International Symposium on Circuits and Systems (ISCAS 1999), May 30 - June 2, 1999, Orlando, Florida, USA. pages 565-568, IEEE, 1999. [doi]

@inproceedings{WuCNGLB99,
  title = {A monolithic 1.25 Gbits/sec CMOS clock/data recovery circuit for fibre channel transceiver},
  author = {L. Wu and H. Chen and S. Nagavarapu and Randall L. Geiger and E. Lee and W. Black},
  year = {1999},
  doi = {10.1109/ISCAS.1999.780816},
  url = {http://doi.ieeecomputersociety.org/10.1109/ISCAS.1999.780816},
  researchr = {https://researchr.org/publication/WuCNGLB99},
  cites = {0},
  citedby = {0},
  pages = {565-568},
  booktitle = {International Symposium on Circuits and Systems (ISCAS 1999), May 30 - June 2, 1999, Orlando, Florida, USA},
  publisher = {IEEE},
  isbn = {0-7803-5471-0},
}