Architecture Exploration and Delay Minimization Synthesis for SET-Based Programmable Gate Arrays - researchr publication authors

researchr

You are not signed in
Sign in
Sign up

Chia-Cheng Wu, Kung-Han Ho, Juinn-Dar Huang, Chun-Yao Wang. Architecture Exploration and Delay Minimization Synthesis for SET-Based Programmable Gate Arrays. In 2018 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018, Hong Kong, China, July 8-11, 2018. pages 257-262, IEEE Computer Society, 2018. [doi]

This author has not been identified. Look up 'Chia-Cheng Wu' in GoogleThis author has not been identified. Look up 'Kung-Han Ho' in GoogleThis author has not been identified. Look up 'Juinn-Dar Huang' in GoogleThis author has not been identified. Look up 'Chun-Yao Wang' in Google

runs on WebDSL