Architecture Exploration and Delay Minimization Synthesis for SET-Based Programmable Gate Arrays - researchr publication

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Chia-Cheng Wu, Kung-Han Ho, Juinn-Dar Huang, Chun-Yao Wang. Architecture Exploration and Delay Minimization Synthesis for SET-Based Programmable Gate Arrays. In 2018 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018, Hong Kong, China, July 8-11, 2018. pages 257-262, IEEE Computer Society, 2018. [doi]

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