An Architecture-Level Energy and Area Estimator for Processing-In-Memory Accelerator Designs

Yannan Nellie Wu, Vivienne Sze, Joel S. Emer. An Architecture-Level Energy and Area Estimator for Processing-In-Memory Accelerator Designs. In IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2020, Boston, MA, USA, August 23-25, 2020. pages 116-118, IEEE, 2020. [doi]

Abstract

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