Bing-Chen Wu, I-Chyn Wey. Parallel Balanced-Bit-Serial Design Technique for Ultra-Low-Voltage Circuits With Energy Saving and Area Efficiency Enhancement. IEEE Trans. on Circuits and Systems, 65-I(1):141-153, 2018. [doi]
@article{WuW18-0,
title = {Parallel Balanced-Bit-Serial Design Technique for Ultra-Low-Voltage Circuits With Energy Saving and Area Efficiency Enhancement},
author = {Bing-Chen Wu and I-Chyn Wey},
year = {2018},
doi = {10.1109/TCSI.2017.2719283},
url = {https://doi.org/10.1109/TCSI.2017.2719283},
researchr = {https://researchr.org/publication/WuW18-0},
cites = {0},
citedby = {0},
journal = {IEEE Trans. on Circuits and Systems},
volume = {65-I},
number = {1},
pages = {141-153},
}