Systolic VLSI realization of a novel iterative division algorithm over GF(2m): a high-speed, low-complexity design - researchr publication authors

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Chien-Hsing Wu, Chien-Ming Wu, Ming-Der Shieh, Yin-Tsung Hwang. Systolic VLSI realization of a novel iterative division algorithm over GF(2m): a high-speed, low-complexity design. In International Symposium on Circuits and Systems (ISCAS 2001), 6-9 May 2001, Sydney, Australia. pages 33-36, IEEE, 2001. [doi]

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