Chien-Hsing Wu, Chien-Ming Wu, Ming-Der Shieh, Yin-Tsung Hwang. Systolic VLSI realization of a novel iterative division algorithm over GF(2m): a high-speed, low-complexity design. In International Symposium on Circuits and Systems (ISCAS 2001), 6-9 May 2001, Sydney, Australia. pages 33-36, IEEE, 2001. [doi]
@inproceedings{WuWSH01,
title = {Systolic VLSI realization of a novel iterative division algorithm over GF(2m): a high-speed, low-complexity design},
author = {Chien-Hsing Wu and Chien-Ming Wu and Ming-Der Shieh and Yin-Tsung Hwang},
year = {2001},
doi = {10.1109/ISCAS.2001.922162},
url = {http://doi.ieeecomputersociety.org/10.1109/ISCAS.2001.922162},
tags = {design complexity, design},
researchr = {https://researchr.org/publication/WuWSH01},
cites = {0},
citedby = {0},
pages = {33-36},
booktitle = {International Symposium on Circuits and Systems (ISCAS 2001), 6-9 May 2001, Sydney, Australia},
publisher = {IEEE},
isbn = {0-7803-6685-9},
}