A 7 bit 800MS/S SAR ADC with background offset calibration

Chao Wu, Jie Yuan. A 7 bit 800MS/S SAR ADC with background offset calibration. In IEEE International Symposium on Circuits and Systems, ISCAS 2016, Montréal, QC, Canada, May 22-25, 2016. pages 1038-1041, IEEE, 2016. [doi]

@inproceedings{WuY16-9,
  title = {A 7 bit 800MS/S SAR ADC with background offset calibration},
  author = {Chao Wu and Jie Yuan},
  year = {2016},
  doi = {10.1109/ISCAS.2016.7527421},
  url = {http://dx.doi.org/10.1109/ISCAS.2016.7527421},
  researchr = {https://researchr.org/publication/WuY16-9},
  cites = {0},
  citedby = {0},
  pages = {1038-1041},
  booktitle = {IEEE International Symposium on Circuits and Systems, ISCAS 2016, Montréal, QC, Canada, May 22-25, 2016},
  publisher = {IEEE},
  isbn = {978-1-4799-5341-7},
}