Parity-based on-line detection for a bit-parallel systolic dual-basis multiplier over GF(2:::m:::)

Parity-based on-line detection for a bit-parallel systolic dual-basis multiplier over GF(2:::m:::). In International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece. IEEE, 2006. [doi]

Abstract

Abstract is missing.