A 128 Kb DAC-less 6T SRAM computing-in-memory macro with prioritized subranging ADC for AI edge applications

Kanglin Xiao, Xiaoxin Cui, Xin Qiao, Xin'an Wang, Yuan Wang 0001. A 128 Kb DAC-less 6T SRAM computing-in-memory macro with prioritized subranging ADC for AI edge applications. Microelectronics Journal, 126:105506, 2022. [doi]

@article{XiaoCQWW22,
  title = {A 128 Kb DAC-less 6T SRAM computing-in-memory macro with prioritized subranging ADC for AI edge applications},
  author = {Kanglin Xiao and Xiaoxin Cui and Xin Qiao and Xin'an Wang and Yuan Wang 0001},
  year = {2022},
  doi = {10.1016/j.mejo.2022.105506},
  url = {https://doi.org/10.1016/j.mejo.2022.105506},
  researchr = {https://researchr.org/publication/XiaoCQWW22},
  cites = {0},
  citedby = {0},
  journal = {Microelectronics Journal},
  volume = {126},
  pages = {105506},
}