A Parallel and Updatable Architecture for FPGA-Based Packet Classification With Large-Scale Rule Sets

Yao Xin, Wenjun Li, Gaogang Xie, Yang Xu 0010, Yi Wang 0004. A Parallel and Updatable Architecture for FPGA-Based Packet Classification With Large-Scale Rule Sets. IEEE Micro, 43(2):110-119, March - April 2023. [doi]

Abstract

Abstract is missing.