Dingxin Xu, Zezheng Liu, Yifeng Kuai, Hongye Huang, Yuncheng Zhang, Zheng Sun, Bangan Liu, Wenqian Wang, Yuang Xiong, Junjun Qiu, Waleed Madany, Yi Zhang, Ashbir Aviat Fadila, Atsushi Shirane, Kenichi Okada. 10.3 A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving -62.1dBc Fractional Spur and 143.7fs Integrated Jitter. In IEEE International Solid-State Circuits Conference, ISSCC 2024, San Francisco, CA, USA, February 18-22, 2024. pages 192-194, IEEE, 2024. [doi]
@inproceedings{XuLKHZSLWXQMZFSO24,
title = {10.3 A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving -62.1dBc Fractional Spur and 143.7fs Integrated Jitter},
author = {Dingxin Xu and Zezheng Liu and Yifeng Kuai and Hongye Huang and Yuncheng Zhang and Zheng Sun and Bangan Liu and Wenqian Wang and Yuang Xiong and Junjun Qiu and Waleed Madany and Yi Zhang and Ashbir Aviat Fadila and Atsushi Shirane and Kenichi Okada},
year = {2024},
doi = {10.1109/ISSCC49657.2024.10454284},
url = {https://doi.org/10.1109/ISSCC49657.2024.10454284},
researchr = {https://researchr.org/publication/XuLKHZSLWXQMZFSO24},
cites = {0},
citedby = {0},
pages = {192-194},
booktitle = {IEEE International Solid-State Circuits Conference, ISSCC 2024, San Francisco, CA, USA, February 18-22, 2024},
publisher = {IEEE},
isbn = {979-8-3503-0620-0},
}