A 3.3-GHz 4.6-mW Fractional-N Type-II Hybrid Switched-Capacitor Sampling PLL Using CDAC-Embedded Digital Integral Path with -80-dBc Reference Spur - researchr publication

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Zule Xu, Masaru Osada, Tetsuya Iizuka. A 3.3-GHz 4.6-mW Fractional-N Type-II Hybrid Switched-Capacitor Sampling PLL Using CDAC-Embedded Digital Integral Path with -80-dBc Reference Spur. In 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021. pages 1-2, IEEE, 2021. [doi]

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