A low-latency fine-grained dynamic shared cache management scheme for chip multi-processor

Jinbo Xu, Weixia Xu, Zhengbin Pang. A low-latency fine-grained dynamic shared cache management scheme for chip multi-processor. In 34th IEEE International Performance Computing and Communications Conference, IPCCC 2015, Nanjing, China, December 14-16, 2015. pages 1-7, IEEE, 2015. [doi]

Abstract

Abstract is missing.