Jinbo Xu, Weixia Xu, Kefei Wang, Zhengbin Pang. Low-latency last-level cache structure based on grouped cores in Chip Multi-Processor. In IEEE 33rd International Performance Computing and Communications Conference, IPCCC 2014, Austin, TX, USA, December 5-7, 2014. pages 1-2, IEEE, 2014. [doi]
Abstract is missing.