All Digital Dividing Ratio Changeable PLL Using Delay Clock Pulse with Low Jitter

Mitsutoshi Yahara, Kuniaki Fujimoto, Hirofumi Sasaki, Takashi Shibuya, Yoshinori Higashi. All Digital Dividing Ratio Changeable PLL Using Delay Clock Pulse with Low Jitter. IEICE Transactions, 89-A(6):1527-1532, 2006. [doi]

Abstract

Abstract is missing.